This invention relates generally to techniques and devices for protecting electronic circuits from high voltage spikes resulting from electrostatic discharges from handling of packaged integrated circuits.
From the beginning of metal-oxide-silicon (MOS) integrated circuit semiconductor technology, it has been recognized that electrostatic discharges through the circuit that result from human handling of a finished chip product can permanently affect the operation of the circuit in undesirable ways. Principally, a thin oxide layer that isolates a gate electrode from the substrate of a NMOS field effect transistor can be irreparably ruptured by a voltage spike being applied across it. In many cases, a gate electrode is connected in a signal path to a pin of a packaged integrated circuit, so the possibility of damage occurring during handling is very high, unless some protection circuitry is provided within the package.
The goal in providing such a protection circuit is to shunt the undesired voltage spikes around the sensitive field effect transistors without affecting the operation of the transistor. Early field effect transistors had a relatively thick gate oxide, so simple protection techniques were satisfactory. As the gate oxides have become thinner as part of an improvement in integrated circuit technology, the electrostatic voltage level that could harm the more delicate gate oxide have become significantly lower. As a result, protection circuits have become more complicated in order to assure that only a lower voltage reached the transistor being protected when the circuit was subjected to a high voltage electrostatic discharge spike.
Along with integrated circuit technology developments that decreased the gate oxide thickness, and thus made them more susceptible to damage from handling, the improving technology was allowing the size of integrated circuits to be shrunk in order to increase the number of circuits that can be produced at one time on a single wafer. The one circuit part that could not be shrunk was the bonding pad since a certain amount of area is required for bonding leads to the circuit chip. If a complicated electrostatic discharage circuit is provided with each input pad, limitations are presented in packing the pads together, and otherwise shrinking the circuit in order to take full advantage of improving process technology.
Accordingly, it is a primary object of the present invention to provide a circuit and integrated circuit layout for reducing any undesired electrostatic voltage spikes to a level that is not harmful to present thin gate oxide field effect transistors.
It is another object of the present invention to provide such a protection circuit and layout that takes very little area of an integrated circuit chip and does not limit the density of components that otherwise may be formed on the chip.
It is a further object of the present invention to provide such protection without adversely affecting the operation of the circuit which is being protected, particularly to maintain reliability and speed of operation of the circuit.